The present invention relates to a semiconductor integrated circuit device and, more particularly, to a testing circuit for a semiconductor integrated circuit device employing a scan pass.
The integration of a semiconductor integrated circuit device has been remarkably improved by the progress microminiaturization techniques and can be expected to be further enhanced in future. The difficulty of testing semiconductor integrated circuit devices has been exponentially increased as this integration (number of gates) has increased. The ease of testing the semiconductor integrated is determined by two points of the ease (observance) of observing the defect of each terminal and the ease (controllability) of setting each terminal to a desired logic value. Deep terminals of large-scale logic circuit network become in general difficult in both observance and controllability.
Scan testing systems for testing semiconductor integrated circuit devices are known as scan testing systems, which improve the observance and the controllability of the deep terminals of large-scale logic circuit networks observe large-scale logic circuit network by inserting register circuits each including a shift register function into proper positions of the logic circuit network, connecting the register circuits by one shift register pass, serially inputting a test pattern from the exterior of a chip at testing time to set predetermined data in the registers, applying a desired logic signal to the logic circuit connected to the data output terminals of the registers to operate the logic circuit, inputting the result from the parallel input terminals of the registers in parallel in the registers, and then serially outputting them out of the chip to observe them.
A fundamental idea of a scan testing system regarding a level sensitive synchronizer circuit is disclosed in Japanese Patent Laid-open No. 28614/1977.
Since the circuit to be observed includes an asynchronous sequential circuit here, the scan testing system will be described with reference to Japanese Patent Laid-open No. 74668/1981 as a prior art.
FIG. 3 shows a prior-art example of a scan pass type testing circuit type with an asynchronous sequential circuit to be observed. In FIG. 3, reference numerals 35 and 37 denote blocks of combination circuits, numeral 36 denotes an asynchronous circuit block including a sequential circuit, numerals 8 to 16 denote scan registers provided between the circuit blocks, and numerals 26 to 34 denote data selectors for selecting any of the outputs of the corresponding circuit blocks and the outputs of the scan registers to output the selected output. The output signals of the respective circuit blocks are connected directly to the data input terminals D of the scan registers and the data input terminals D of the data selectors, respectively, and the output terminals Q of the corresponding scan registers are connected to the test data input terminals TD of the data selectors, respectively.
In FIG. 1, reference numeral 1 denotes a test mode selection terminal, which is connected to the mode selection terminals MS of the scan registers and the data selectors, respectively. Numeral 2 denotes a scan-in terminal, and numeral 38 denotes a scan-out terminal. The scan-in terminal 2 is connected to the scan-in terminal SI of the scan register 8, and the output terminal Q of the scan register 8 is connected to the scan-in terminal SI of the scan register 9. Thus, the output terminals Q of the respective scan registers are sequentially connected to the scan-in terminals SI of the next scan registers to resultantly form a shift register pass between the scan-in terminal 2 and the scan-out terminal 38. Numerals 3 to 5 denote ordinary data input terminals, numeral 6 denotes a scan clock input terminal, which is connected to the clock input terminals T of the scan registers.
FIG. 4 shows an example of the scan register shown in FIG. 3, symbol MS denotes a mode selection terminal, symbol D denotes a data input terminal, symbol IS denotes a scan-in terminal, and symbol T denotes a clock input terminal. Numeral 151 denotes an inverter gate, numerals 152 and 153 denote 2-input AND gates, numeral 154 denotes a 2-input OR gate, numeral 155 denotes an edge trigger D type flip-flop (hereinbelow referred to as "D-FF"), and symbol Q denotes a data output terminal.
FIG. 5 shows an example of the data selector shown in FIG. 3. Symbol MS denotes a mode selection terminal, symbol TD denotes a test data input terminal, symbol D denotes a data input terminal, numeral 160 denotes an inverter gate, numerals 161 and 162 denote 2-input AND gates, numeral 163 denotes a 2-input OR gate, and symbol Y denotes an output terminal.
The operation of the scan pass type testing circuit will be described.
The ordinary operation will be first described. In this case, a signal "H" is applied to the test mode selection terminal 1 (MS), and the scan clock terminal 6 (TS or T) is fixed to a voltage "L". As a result, the input and output terminals of the corresponding circuit blocks are connected directly through the respective data selectors.
This operation will be described with reference to FIG. 5. When a signal "H" is applied to the mode selection terminal MS of the data selector, the data from the data input terminal D is outputted through the AND gate 162 and the OR gate 163 to the output terminal Y. Since the output of the circuit block is connected directly to the data input terminal D of this data selector, the input and output terminals of the corresponding circuit block are connected directly.
The scan mode and the test mode are sequentially repeated as below at testing time to test the respective circuit blocks.
(1) Scan Mode
(a) A signal "H" is applied to the test mode selection terminal 1 to set the scan mode. Thus, the scan register selects the input data from the scan-in terminal Si, and the data selector validates the input data from the data input terminal D.
(b) Further, the test data set in the respective scan registers from the scan-in terminal 2 are sequentially scanned in synchronously with the clock applied to the scan clock terminal 6.
(c) Simultaneously the output data inputted to the respective circuit blocks at the previous testing time are sequentially scanned out from the scan-out terminal 38.
This operation will be described with reference to FIGS. 4 and 5. When a signal "H" is first applied to the mode selection terminal MS of the scan register, the data from the scan-in terminal SI is held in D-FF 55 synchronously with the clock applied to the clock terminal T through the AND gate 153 and the OR gate 154, and the data held simultaneously is output from the output terminal Q. The signal "H" is also applied to the mode selection terminal MOS of the data selector at this time, and the data from the data input terminal is outputted to the output terminal Y.
(2) Test Mode
(a) After the desired data are set in the respective scan registers, a voltage "L" is applied to the test mode selection terminal 1 to set a test mode.
(b) Thus, the output data of the scan register is applied through the test data input terminal TD of the data selector to the respective circuit blocks.
(c) Simultaneously, the desired test data are applied to the data input terminals 3 to 5.
(d) When the operations of the circuit blocks have been completed, a clock is applied to the scan clock input terminal 6. Thus, the output signals of the respective circuit blocks are held in D-FF in the scan registers through the data input terminals D of the corresponding scan registers.
These operations will be described with reference to FIGS. 4 and 5. When a voltage "L" is first applied to the mode selection terminal MOS of the scan register, the data from the data input terminal D is held in D-FF 155 synchronously with the clock applied to the clock input terminal T through the AND gate 152 and the OR gate 154. Since the voltage "L" is also applied to the mode selection terminal MOS of the data selector at this time, the data from the test data input terminal TD is outputted to the output terminal Y through the AND gate 161 and the OR gate 163.
Thus, the respective circuit blocks can be tested. The data selectors in the circuits select the output data of the respective circuit blocks during the scanning operation. In this manner, even if the output value of the scan register is sequentially varied during the scanning operation, the state of the circuit block 35 including the sequential circuit is inhibited to vary. Therefore, even if the circuit block surrounded by the scan pass is the asynchronous sequential circuit as in this example, the scanning test can be performed.
Since the conventional scan testing system is constructed as described above, the system can execute the scan test for the block including the asynchronous sequential circuit. However, when the test mode is switched to the scan mode, the data applied to the sequential circuit is generally varied from the serially inputted signal value to the output signal value of the adjacent circuit block. Thus, it is difficult to set the input so that the state of the asynchronous sequential circuit to be observed may not vary. In many cases, there arises a drawback that the scan test cannot be effectively carried out.